An analog-to-digital converter (“ADC”) is often a critical component in the determination of overall performance for various digital electronic devices. Additionally, as more and more electronic products are being developed as hand-held devices, the power consumption of ADCs is often a critical design element for devices that utilize relatively low power. In conventional devices, the architecture of an ADC is typically determined by evaluating required power consumption, resolution, and sampling frequency parameters. For low-power performance, a successive-approximation type ADC is typically utilized.
However, if higher resolution performance is required, other type of ADCs, such as pipelined or sigma-delta ADCs, are often utilized. These higher resolution ADCs sacrifice low-power characteristics. Recently, significant research has been conducted in attempts to reduce the power consumption of higher resolution ADCs; however, acceptable power consumption levels for hand-held devices (e.g., μW-level power) have not been achieved. Accordingly, improved analog-to-digital converters are desirable.